Update on MKHBC-8-R2 6502 computer - prototyping banked RAM - revision 2.

I promised an update when I figure out the solution to my problem with RAM bank switching side effect when reading from the I/O mapped area $C000..$C0FF.
Well, I think I fixed it, but the glue logic is a bit more elaborate than I expected. Since the desired function was to generate rising edge on CLK input of 74LS374 latch only when /IO0 = 0 and R/W = 0 and Phi2 goes from HI to LO, I had to come up with the circuit with following truth table:

/IO0    R/W   Phi2    |    CLK
----------------------------------
  0      0      0     |     1
  0      0      1     |     0
  0      1      0     |     0
  0      1      1     |     0
  1      0      0     |     0
  1      0      1     |     0
  1      1      0     |     0
  1      1      1     |     0
----------------------------------

I'm sure you can see a familiar pattern here. This is like 3-input AND with output flipped over. Above function is realized with 3-input AND with its inputs negated:

Since I have no IC with 3-input AND, I transformed that circuit to NAND-s only equivalent and came up with this:

It looks like I will be needing this extra 74LS00 chip that I saved (see my previous blog update). Here is the final circuit for banked RAM:

Now the bank register is not switching to bank 0 when reading operation is performed on address from I/O 0 range ($C000..$C0FF).

2/7/2016
M.K.