In my first post about MKHBC-8-R1 I mentioned that I would consider two architectures. One with passive motherboard and expansion sockets, to which self address-selected and self buffered cards would be plugged and the other with CPU and address selection circuits on mobo and buffered I/O expansion bus. Today I decided that I will go with active motherboard with clocks, CPU, IRQ controller, address and I/O decoding and two expansion buses - one for memory/video cards (non-buffered CPU bus with 2 or 3 euro bus type sockets) and second bus for I/O devices like data input/output ports, serial/parallel ports, perhaps a sound card (it is going to be a buffered bus with 6 expansion sockets, I will probably use IDE connectors, one set of bi-directional buffers made with 74LS245 chips, with total of 24 lines: 8 address lines A0-A7, 8 data lines and some control signals). Each of the I/O expansion sockets will have one pin connected to one of the I/O selection lines from I/O address decoder (so each will have its own 256 bytes long address space) and one pin connected to one of the inputs of interrupt controller. For interrupt controller I decided to use circuit proposed by Paul Fellingham. It is simple and elegant. I just needed to add some glue logic to incorporate it into my design (the interrupt controller has one read and one write port so it is I/O device which I need to put in dedicated address space).
I do not expect memory or graphics card to be an interrupt source, so the CPU non-buffered bus will not have interrupt pins assigned, however it will have full address bus and all CPU control signals on it. I also buffered phase 2 signal from CPU (2 inverters). I built the I/O expansion bus buffer circuit on a bread board and attached my only (for now) I/O device (6850 based UART/serial port) to it (it was previously on CPU bus). It seems to be working fine. I am able to communicate with my computer over serial connection, send and receive data etc. The real test (and fun) will commence when I build the interrupt controller and attach more devices to the I/O expansion bus. Then I will see if there are no conflicts on the bus and timing issues and such. I updated my schematics which are available online in PDF format (sorry, they are still hand drawings, one day I will draw them in some circuit drawing program, for now this will have to suffice).
Figure 1: The lower small bread board is an I/O expansion bus buffer circuit.
The upper board is 6850 UART connected to the I/O Expansion Bus.
At the top of picture is a MAX 232 module board I got on e-bay and serial to USB converter (also from e-bay) which allows to connect MKHBC to my PC's USB port.
CPU sits in right lower corner on the big bread board.
EPROM chips are located mid-upper left below LEDs.
RAM (32kB) is located to the right side of EPROMs (above it is 7805 5V regulator).
Just a bit to the left of RAM chip is I/O decoder circuit.
Below EPROMS is main I/O selection and EPROM selection address decoding circuit.
To the left of CPU are clock and reset circuits and some glue logic.
The whole prototype consists of 16 ICs now (not counting can oscillators, which are 2, one for CPU and future video card and one for Tx, Rx speed of 6850 uart). Not that many, considering this is going to be general purpose computer system, however there will be much more (probably double current amount) with all the expansion cards that I plan to build. I probably need to consider using more capable power supply (currently I just use universal 1500 mA wall socket power adapter and single 7805 5V regulator. It (7805 with small radiator) gets pretty hot while working (but not sizzling yet).
That's all for today, folks! Thanks for reading.